Regviz

Espressif Systems /ESP32-S2 /RTC_CNTL /ULP_CP_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ULP_CP_CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S2/RTC_CNTL/ULP_CP_CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ULP_CP_MEM_ADDR_INIT0ULP_CP_MEM_ADDR_SIZE0 (ULP_CP_MEM_OFFSET_CLR)ULP_CP_MEM_OFFSET_CLR 0 (ULP_CP_CLK_FO)ULP_CP_CLK_FO 0 (ULP_CP_RESET)ULP_CP_RESET 0 (ULP_CP_FORCE_START_TOP)ULP_CP_FORCE_START_TOP 0 (ULP_CP_START_TOP)ULP_CP_START_TOP

Description

ULP-FSM configuration register

Fields

ULP_CP_MEM_ADDR_INIT
ULP_CP_MEM_ADDR_SIZE
ULP_CP_MEM_OFFSET_CLR
ULP_CP_CLK_FO

ULP-FSM clock force on
ULP_CP_RESET

ULP-FSM clock software reset
ULP_CP_FORCE_START_TOP

Write 1 to start ULP-FSM by software
ULP_CP_START_TOP

Write 1 to start ULP-FSM

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data